Large die photolithography

ABSTRACT

An improved reticle ( 20 ) and method of using it to expose layers of wafers for large integrated circuits ( 10 ). The integrated circuit ( 10 ) is designed so that nonrepeating patterns are laid out in perimeter areas, distinct from the center area containing contiguous repeating patterns. The reticle ( 20 ) is patterned with multiple masks ( 21-23 ), with different masks representing the repeating and nonrepeating patterns. The mask ( 22 ) representing the repeating pattern may then be stepped and illuminated separately from any mask ( 21, 23 ) representing a nonrepeating pattern.

TECHNICAL FIELD OF THE INVENTION

The invention relates to integrated electronic circuits, and moreparticularly to fabricating devices having repeatable patterns.

BACKGROUND OF THE INVENTION

Fabrication of integrated circuits requires precisely controlled sizingof areas to be doped, etched, or otherwise processed. Photolithographictechniques are often used for defining these areas. That is, aphotoresist layer is first applied to a substrate, and then exposedthrough a mask. The mask contains clear and opaque features that definethe pattern to be created in the photoresist layer. The areas in thephotoresist that are exposed to light, or other radiation, are madeeither soluble or insoluble in a solvent known as a developer. When theexposed regions are soluble, a positive image of the mask is produced inthe resist. When the nonexposed regions are soluble, a negative imageresults. After developing, the regions of the substrate no longercovered by the resist are removed by etching, thus replicating the maskpattern on the substrate.

In modern fabrication plants, wafers are formed from a number ofidentical dies, which each eventually become an integrated circuit. A“reticle” is a glass emulsion or chrome plate having an enlarged imageof a single die. The photolithographic equipment steps and repeats thereticle across the wafer, with each step exposing one integratedcircuit.

Many of today's integrated circuits have patterns that repeat, but whoserepeating areas are too large to be contained on a single reticle. Inother words, the size of the repeatable pattern exceeds the printablearea of conventional lithographic equipment, so that the printing cannotbe accomplished by stepping and repeating a single reticle. For example,a typical upper limit on reticle size is in the range of 22 millimeterssquare. Yet, for modern integrated circuits, it might be desired to havea repeatable pattern that exceeds this size.

Another problem with applying existing step and repeat processes is thatmany of today's circuits are so functionally sophisticated that a singlechip may contain several types of circuits, which differ as torepeatability as compared to the other circuitry on the chip. Forexample, a memory device might have control circuitry as well as amemory cell array, with an overall pattern that repeats on a largerscale than the size of a single reticle.

One approach to exposing pattern sizes that exceed the size of a reticleis to use a “composition reticle”. For example, a doubled pattern sizecan be accomplished if two reticles are used for the same layer, at twodifferent times to step and repeat in alternating areas on the wafersurface. However, alignment of the two stepping processes is difficultand the processing time is increased.

A need exists for a fabrication process that facilitatesphotolithography for large and complex integrated circuits.

SUMMARY OF THE INVENTION

One aspect of the invention is a reticle for fabricating an integratedcircuit on a wafer. As with conventional reticles, the reticle is formedby patterning opaque features on a transparent substrate. However,unlike conventional reticles, the reticle divides the circuit patterninto more than one mask. For example, the reticle might have onenonrepeating mask and one repeating mask. The nonrepeating mask is usedonce for exposing a first sub-pattern, while the repeating mask isblocked. Then, the nonrepeating mask is blocked and the repeating maskis used in a series of steps to expose a number of second sub-patterns.

A technical advantage of the invention is that alignment is a functionof the accuracy of the step positioning capability of the lithographicequipment, without the added problem of aligning two different reticles.Typical lithographic step positioning is accurate within 0.02 to 0.03micrometers, which is acceptable for today's circuit tolerances.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a top plan view of a fabrication layer of a semiconductorwafer, with components laid out in accordance with the invention.

FIG. 2 is a top plan view of a reticle having separate mask areas inaccordance with the invention.

FIG. 3 illustrates a reticle for a memory device.

FIG. 4 illustrates a reticle for a deformable mirror device.

DETAILED DESCRIPTION OF THE INVENTION

Although the following description is in terms of fabricating anintegrated circuit, the same description would be applicable to anyother device made by photolithographic techniques. A commoncharacteristic of such devices is that they require substantialprecision in the formation of their components, and have a large arrayof repeating components. The “circuits” would be some other set ofcomponents. For example, liquid crystal display devices are made withphotolithographic techniques, and could be made by using the reticledescribed herein.

FIG. 1 is a top plan view of a fabrication layer of a wafer 10, having apattern of 15 dies, each of which will become an integrated circuit 10a,with components laid out in accordance with the invention. Morespecifically, the components of circuit 10a are laid out with threetypes of areas, each having a pattern with a different repeatability.

In the example of this description, the layer of wafer 10 has threedifferent patterns. A first pattern is laid out in area 11, a secondpattern in area 12, and a third pattern in area 13. The first and thirdareas 11 and 13 have nonrepeating patterns; the second area 12 has anumber of repeating patterns.

In terms of the circuits that the patterns represent, peripheralsubcircuits 11 and 13 are laid out at both ends, and individuallycomprise a left peripheral subcircuit 11 and a right peripheralsubcircuit 13. These circuits have nonrepeating patterns, in the sensethat each appears only once. Repeatable subcircuits 12 comprise themiddle portion of the layer of circuit 10a. Repeatable subcircuits 12are contiguous, have equal size, and are internally identical to eachother. In the example of this description, circuit 10a has threerepeatable subcircuits 12.

Typical components that might be patterned within left and rightperipheral subcircuits 11 and 13 are address circuitry, built-in selftest circuitry, clock counters, and control logic. Typical componentsthat might be patterned within each repeatable subcircuit 12 are logicgate arrays and memory cell arrays.

FIG. 2 is a top plan view of a reticle 20, having separate masks 21-23in accordance with the invention. As in conventional reticles, reticle20 is patterned from a substrate of transparent material, such as glass.The patterning of each mask 21-23 is accomplished by conventionalmethods, resulting in each mask 21-23 having its own unique pattern ofopaque and transparent features, that either block or transmit light totransfer the same pattern to the surface of a wafer.

A left mask 21 contains the pattern for left peripheral subcircuit 11. Arepeatable mask 22 contains the pattern for each repeatable subcircuit12. A right mask 23 contains the pattern for right peripheral subcircuit13.

Although FIG. 2 shows the arrangement of mask areas 21-23, relative toeach other, as being the same as the arrangement of their correspondingpatterns on wafer 10, they could be arranged otherwise. For example,reticle 20 might have left mask 21, then right mask 23, then repeatableunit mask 22, in that order, from left to right.

The depiction of masks 21 and 23 as nonrepeating and mask 22 asrepeating is for example only. More than one of masks 21-23 could berepeating. As explained below, the important characteristic of reticle20 is that it has different masks for different patterns havingdifferent repeatability, such that during exposure, all masks other thana selected mask can be blocked and only the selected mask used forexposing the wafer 10 in a series of contiguous steps. This blocking iseasily accomplished by using shuttering features available onconventional lithographic equipment.

FIGS. 1 and 2 illustrate two nonrepeating patterns 11 and 13 and theircorresponding masks 21 and 23 at the left and right peripheries of thecircuit 10a. However, the same principles would apply if thenonrepeating patterns were at the top or bottom of the circuit 10a.

In operation, reticle 20 is used to expose all areas of a layer on wafer10. For each die, reticle 20 is first placed at an initial position toexpose the left peripheral subcircuit 11 with the left mask 21. At thistime, only the left mask 21 transmits light to expose the surface ofwafer 10; masks 22 and 23 are shuttered off or otherwise blocked so thatthey do not transmit light.

Then, reticle 20 is stepped, relative to the surface of wafer 10, anappropriate distance to the right, and blocked so that only mask 22transmits light to wafer 10. Reticle 20 is illuminated and stepped anumber of times to expose a first repeatable subcircuit 12, then asecond repeatable circuit 12, etc., for as many times as required toexpose an entire array of repeatable subcircuits 12 on wafer 10.Finally, the reticle 20 is stepped into position to expose the rightperipheral subcircuit 13 with the right mask 23. The stepping of theabove process differs from that of conventional step and repeatprocesses in that each stepping movement is in accordance with the masksize rather than the reticle size.

The above description is in terms of a single die, i.e., a portion ofwafer 10 that will result in a single integrated circuit device. Thesame process is repeated for each die on the wafer 10.

FIG. 3 illustrates a reticle 30 for exposing layers of a memory device,fabricated as an integrated circuit. Column addressing subcircuitry androw addressing subcircuitry are represented in the patterns of top mask31 and left mask 33, respectively. The memory cell array is formed bystepping and repeating a repeatable memory cell mask 42, whose patternrepresents a unit of one or more memory cells.

FIG. 4 illustrates a reticle 40 for exposing layers of a deformablemirror device (DMD), another device whose manufacture is especially madeeasier by the invention. In general, DMDs are a type of spatial lightmodulator having an array of pixel elements, which are tinymicro-mechanical mirrors. The pixel elements are individuallyaddressable, such that each can be selectively positioned to directlight in either an “on” or “off” position. An addressed array of pixelelements represents an image frame, with the image being formed as aresult of which pixel elements direct light to the image plane. Theimage can be captured by means of opto-electrical devices and used togenerate a display or printed copy.

Typically, the pixel elements of a DMD have associated memory cells forstoring the binary signal that will drive the pixel element to its on oroff position. An advantage of many DMD designs is that the pixel array,as well as the memory cells and addressing circuits can be fabricatedwith integrated circuit techniques.

As the resolution provided by the DMD increases, so does the number ofpixel elements in the pixel element array. Because of the large numberof pixel elements, the overall size of the DMD may easily exceed themaximum reticle size for patterning with conventional photolithographicequipment. For example, a high resolution DMD for display or printingapplication might have a length in the order of 3 or 4 inches.

FIG. 4 illustrates masks 41-43 for a DMD is laid out with left and rightperipheral circuits as in FIG. 1. U.S. patent Ser. No. 07/678,761,entitled “DMD Architecture and Timing for Use in a Pulse-Width ModulatedDisplay System”, describes a DMD device having circuitry that may belaid out in this manner, and is incorporated herein by reference.

Masks 41-43 accommodate large DMDs by permitting fabrication inaccordance with the invention. Left mask 41 and right mask 43 containrow address circuitry and control logic. The repeatable mask 42 containssubarrays of patterns for the pixel elements. These masks 41-43 arepositioned and illuminated in the manner described above in connectionwith FIGS. 1 and 2.

For fabricating a linear DMD array, additional components, such as inputregisters could be included in the repeatable mask 42. For a squarearray, these input registers could be fabricated with upper and lowermasks, as in FIG. 3, in addition to masks 41-43.

Other Embodiments

Although the invention has been described with reference to specificembodiments, this description is not meant to be construed in a limitingsense. Various modifications of the disclosed embodiments, as well asalternative embodiments, will be apparent to persons skilled in the art.It is, therefore, contemplated that the appended claims will cover allmodifications that fall within the true scope of the invention.

What is claimed is:
 1. A reticle for exposing a layer of a device madeby photolithographic techniques, comprising: a transparent substrate; anonrepeating mask on said substrate, having a first pattern for exposinga nonrepeating set of components; and a repeating mask patterned on saidsubstrate, having a second pattern for exposing a contiguously steppedset of repeating components, wherein said nonrepeating set of componentsis contiguous with and allows connection between itself and at least oneof said set of repeating components on one chip.
 2. The reticle of claim1, wherein said nonrepeating mask represents a set of components in aperimeter of the device.
 3. The reticle of claim 1, wherein saidrepeating mask represents a portion of an array of identical componentsin the center of the device.
 4. A reticle for exposing at least onelayer of a semiconductor wafer, comprising: a transparent substrate; anonrepeating mask patterned on said substrate, having a first patternfor exposing a nonrepeating subcircuit; and a repeating mask patternedon said substrate, having a second pattern for exposing a contiguouslystepped set of repeating subcircuits on the center portion of saidwafer, wherein said nonrepeating subcircuit is contiguous with andallows connection between itself and at least one of said set ofrepeating subcircuits on one chip.
 5. The reticle of claim 4, whereinsaid nonrepeating mask has pattern that represents peripheral controlsubcircuitry at a perimeter of the integrated circuit.
 6. The reticle ofclaim 4, and further comprising an another nonrepeating mask on saidsubstrate, having a third pattern for exposing another subcircuitpattern at a perimeter of the integrated circuit.
 7. The reticle ofclaim 6, wherein said nonrepeating masks are on opposing sides of theintegrated circuit.
 8. The reticle of claim 6, wherein said nonrepeatingmasks are on adjacent sides of the integrated circuit.
 9. The method ofclaim 8 12, wherein said blocking step is performed with shutteringdevices of photolithographic equipment.
 10. The reticle of claim 4,wherein said repeating mask has a pattern that represents memory cells.11. The reticle of claim 4, wherein said repeating mask has a patternthat represents deformable mirror pixel elements.
 12. A method ofexposing wafers made devices with photolithographic stepper equipment,for devices having an array of repeating components whose repeatabilityexceeds the stepping increments of the photolithographic equipment,comprising the steps of: patterning the device into subareas, wherein anonrepeating pattern is laid out in a perimeter area of the device and arepeating pattern is laid out in a center area of the device;fabricating a lithographic reticle for said nonrepeating and repeatingpatterns, such that a single reticle has a nonrepeating mask and arepeating mask; blocking said repeating mask area such that only saidnonrepeating mask area transmits light to said perimeter area;illuminating said reticle to expose the surface of said device with thepattern of said nonrepeating mask; moving said reticle to expose aportion of said center area; blocking said nonrepeating mask such thatonly said repeating mask transmits radiation; and stepping saidrepeating mask a number of times, to expose a number of contiguousrepeating patterns in said center area.